1. Field
One embodiment of the invention relates to a line memory packaging apparatus, and to a television receiver. In particular, the present invention relates to a technique of forming a logical line memory with respect to hardware using several RAM components.
2. Description of the Related Art
A line memory is used for various operators processing video data in a video signal processor. For example, the line memory has a bit width of 8 or 16 bits and a bit length corresponding to the number of pixels equivalent to horizontal one line. A circuit using several line memories is used for converting and changing over vertical resolution. Moreover, several line memories are used as a filtering circuit (e.g., Jpn. Pat. Appln. KOKAI Publication No. H10-340340).
According to the foregoing conventional technique, several line memories is mainly used for processing data delay. Basically, one line memory is handled as a first-in first-out (FIFO) buffer. For this reason, the array number of a first-stage line memory is designed in accordance with the input bit width and input pixels of an operator using an output of several line memories. Several line memories each set a read/write point.